1. Field of the Invention
This invention relates to Class-D amplifier circuits, especially to Pulse-Density-Modulated or Sigma-Delta Class-D amplifiers with an H-bridge output.
2. Description of the Related Art
FIG. 1 shows a basic arrangement of a pulse-density-modulated (PDM) Class-D amplifier, sometimes referred to as a Sigma-Delta amplifier. An output stage 101 comprises four switches connected in an H-bridge arrangement between two supplies, typically a supply voltage Vdd and ground. Feedback signals from the output terminals 102 and 103 of the H-bridge are respectively subtracted from input signals Vin+ and Vin− of the amplifier in order to generate respective error signals which are passed through a loop filter 104, for example an integrator.
The output signal from the loop filter 104 is quantised by a comparator 105 that is clocked to provide a digital control signal at a desired drive frequency FDD. The desired drive frequency FDD is significantly higher than the frequency of the input signals, Vin+ and Vin−, to be amplified and, for an audio amplifier, the desired drive frequency FDD may have a frequency of the order of MHz, for example 3 MHz.
The digital control signal may be passed through optional logic 106 before being received by the pre-driver logic 107 to generate buffered gate drive signals for controlling the switches in the H-bridge output stage 101.
In a basic Class-D amplifier such as illustrated in FIG. 1, the H-bridge output may be operable in two states only, those illustrated as states A and B in FIG. 2: it should be noted that in use a load (not illustrated) is connected between the output terminals 102 and 103 of the H-bridge 101. In continuous state A, assuming the upper rail is at Vdd and the lower rail is at ground, the output voltage across the load, i.e. terminals 102, 103, will settle to +Vdd (ignoring any switch voltage drops). In continuous state B, the voltage across the load will settle to −Vdd. Switching between states A and B with an effective duty of cycle of 50:50 will result in an output that settles to zero and other duty cycles will result in intermediate differential d.c. output voltages. Thus the switch drive signals control the H-bridge output to switch between states A and B as required and the output is averaged by an inductance (possibly an inductance associated with the load) to give low (e.g. audio) frequency components which follow the input signal.
One issue with such a two-state Class-D amplifier is that for low signals the H-bridge output stage 101 will switch between the states A and B at a rapid rate to maintain a low output voltage. Each transition between states will consume power, for example in charging and discharging the relatively large output MOS switch transistors. Also, even for minimal input signals the load will alternate between having +Vdd and −Vdd applied across it, with a consequent alternating ramp of current dI/dt=±Vdd/L, where L is the load inductance. This will lead to substantial ripple current in the load, especially for low load inductance, which will tend to cause power losses. The large differential-mode voltage ripple across the load may also result in consequent EMI problems, especially if the load is somewhat distant from the driver amplifier, i.e. H-bridge output stage 101.
To mitigate these effects the H-bridge output stage 101 may also be operated in a third state, state C as illustrated in FIG. 2. In this state C both output terminals 102, 103 are connected to ground. The comparator 105 of FIG. 1 may therefore be modified to generate three output logic states, which may be regarded as +1, 0, −1 say, by comparing the integrated error signal at the loop filter output against two separate thresholds, for example +Vdd/3 and −Vdd/3. The logic states +1, 0, −1 drive the H-bridge 101 in states A, C, B respectively.
At small signal levels the H-bridge 101 output will usually be in state C, with just the occasional pulse of states A or B to correct the low frequency components of the output voltage. Thus there will be far fewer transitions for low signals with a consequent saving in power. Also since there are fewer transitions, for a given inductance connected to the output the average ripple current will be lower resulting in reduced differential mode EMI. This means that if a certain amount of ripple current is acceptable (for a given signal level), this level of ripple current can achieved using a smaller series inductor than would be the case with just a two state amplifier or indeed just relying on the parasitic inductance of a speaker load.
In such an arrangement however the common-mode output voltage will vary. In both state A and state B the common-mode output voltage is equal to Vdd/2. In state C the common-mode output voltage is zero. Thus, at high signal levels, when the H-bridge 101 will be predominantly in state A or state B the average common-mode output voltage will be at or near Vdd/2. However at low signals the H-bridge 101 will be predominantly in state C and the average common-mode output voltage will be near zero.
Thus if a low-frequency sinusoidal signal of amplitude Vdd is generated at the output of the H-bridge 101, the common-mode voltage will be modulated between zero and Vdd/2. In other words the common-mode voltage will correspond to a full-wave rectified version of the audio input signal Vin, i.e. Vin+, Vin−. Whilst ideally this would not matter, in practice the subtraction of the feedback signal from the input signal at the input to the loop filter 104 will be performed by resistor networks that may suffer from random manufacturing mismatches. Thus the common-mode rejection ratio of the subtractor may be in the region of 40 dB to 60 dB. Modulation of the common-mode voltage in this way can therefore cause spurious differential-mode signal components at the summing point, which the loop filter 104 will cancel by generating a corresponding real differential signal at the output. As the spurious signal contains harmonics of the output sine wave the actual output will also contain opposite harmonic components to cancel this spurious signal and thus harmonic distortion will appear across the load. Also the common-mode modulation may cause generation of signal-dependent common mode EMI.
To avoid these effects, the H-bridge 101 may additionally be operated in a fourth state, state D in FIG. 2. In this state both outputs are connected to Vdd. This state, like state C, thus has a differential output of zero, but the common-mode voltage is Vdd, not zero. The amplifier is then operated such that, in those cycles where a zero differential voltage is desired, i.e. the output of the tri-level comparator is logic 0, logic 106 operates to ensure that each of states C and D is chosen on average for half of those cycles. Thus, just considering the zero states, the average common-mode voltage will be Vdd/2. Since the output common mode voltage in states A and B is also Vdd/2 this means that the output common mode voltage is Vdd/2 independent of output signal and no harmonics are generated.
In this arrangement, however, as the average common-mode output mode is substantially constant at Vdd/2, then if there is any ripple on the power supply the common mode output voltage will exhibit half this ripple. As mentioned above, the common-mode rejection ratio of the subtractor may be only 40 dB to 60 dB and thus the common-mode ripple will result in an unwanted signal component only about 46 dB to 66 dB below the supply ripple which will appear across the load. This may be inadequate in some applications which require a power supply rejection ratio in excess of 80 dB.